The present invention relates to a memory device, an internal control method therefor, a system and a method of memory control in the system.
Recently, the current consumption of semiconductor memories (dynamic RAMs) that need a refresh operation is inclined to increase due to an increase in the memory capacity demanded by clients (system side), an increase in access speed (higher operational frequency), an increase in I/O bus width (an increase in the number of data bits that are handled in one access) and so forth. The increase in the power consumption of memory devices is likely to cause an increase in the total current consumption of a system in which such a memory device is installed. There exists a need, therefore, to reduce power consumption of memory devices.
The increase in current consumption may raise the chip temperature of a memory device. In general, the data retaining characteristic (i.e., refresh characteristic: TREF) of DRAM cells is impaired (the retaining time becomes shorter) at high temperature. From the viewpoint of the data retaining characteristic, therefore, a reduction in current consumption is desired.
That is, semiconductor memories require that both an improvement in performance, such as larger memory capacity, faster access and extension of the I/O bus width, and a reduction in power consumption should be satisfied.
A memory device has a memory cell array having an array of a plurality of memory cells and sense amplifiers. Each memory cell is operatively coupled to one of a plurality of word lines laid out in, for example, the X direction and one of a plurality of bit lines laid out in the Y direction. Each bit line is provided with a sense amplifier which amplifies information (read data) of a single memory cell and retains the information.
In case of the memory capacity of 1 Mbits, the logical address of the memory device includes an X (row) address of, for example, 10 bits (210=1024 word lines WL) and a Y (column) address of 10 bits (210=1024 bit lines BL (1024 sense amplifiers)). (Note: bit line definition=a pair of complementary bit lines). If the layout pitch of the word lines WL is the same as the layout pitch of the bit lines BL in this case, the logical memory array is characterized as having a square shape.
The following will describe the internal operation of an SDRAM (Synchronous DRAM) synchronous to a system clock CLK as an example of a memory device.
An SDRAM operates in accordance with the falling and rising of an activation/precharge command which is synchronous to a system clock CLK and causes the memory device to be active/inactive, and a write/read command for inputting and output data to and from the memory device.
When receiving an activation command from an external device at the rising edge of the system clock CLK, the SDRAM fetches an X address and decodes the X address in an X decoder. In accordance with the decoded X address, a single word line is selected and the selected word line is enabled. A plurality of memory cells connected to the selected word line output data to the respective bit lines and the respective sense amplifiers amplify and retain (latch) the data.
When receiving a read command from the external device at the rising edge of the system clock CLK with a delay of several clocks from the activation command, the SDRAM fetches a Y address and decodes the Y address in a Y decoder. In accordance with the decoded Y address, data held in a single sense amplifier is outputted from the memory device. When receiving a write command from the external device, the SDRAM fetches a Y address and decodes the Y address in the Y decoder. In accordance with the decoded Y address, write data is written in the associated memory cell via a single sense amplifier. Thereafter, a read/write command is executed as needed and access is made to the memory cell that corresponds to a desired Y address and the external device.
After several clocks from the read/write command, the SDRAM receives the precharge command at the rising edge of the system clock CLK. The precharge command resets (equalizes) the enabled word line, sense amplifier and bit lines and the memory array returns to the initial state to be ready for the next activation command.
An internal time is required until the reset operation and a time (wait) of several clocks is needed for application of a next activation command from the reception of the precharge command. Likewise, a time (wait) of several clocks is needed from the activation command to a read/write command.
Although a description has been given of the case where the number of input/output data bits of the memory array is 1 for the sake of descriptive simplicity, n sense amplifiers are enabled simultaneously by a Y address when the number of input/output data bits is n (written as “n I/O” (e.g., 4 I/O)). The n sense amplifiers are respectively connected to n I/O ports via n I/O buses.
The depth of the Y address is called “page length”. The memory device operates sense amplifiers at least equal in number to the I/O bus width×page length in response to a single activation command. In case of an SDRAM whose Y address is set to 8 bits (YA<0:7>), for example, the page length is 256. In case where the SDRAM has an I/O bus width of 32 bits, at least 8192 (=256×32) sense amplifiers operate in response to the activation command.
The SDRAM latches information from a plurality of memory cells connected to the word line that has been selected by the activation command in a plurality of sense amplifiers in accordance with a read command input whenever necessary. As a single word line is enabled, information from memory cells for a page length is properly outputted to an external device. Specifically, a single sense amplifier is selected in accordance with a Y address which accompanies a read/write command supplied as needed, and information is read out from those memory cells which are connected to the selected sense amplifier. With an X address (word line) fixed, the Y address is accessed at random. This operation is called “Y address priority operation”. Likewise, information can be written in the memory cell at an arbitrary Y address through the Y address priority operation in response to a write command.
The Y address priority operation efficiently uses plural pieces of data latched in a plurality of sense amplifiers that have been enabled by a single activation command. 256 memory cells are accessed at random using a single word-line charge/discharge current and a single bit-line charge/discharge current provided by each sense amplifier.
The current that is consumed in a single random access is calculated by dividing the current consumption which is the word-line charge/discharge current plus the bit-line charge/discharge current by the number of accesses in pages that are activated at the same time. Therefore, the greater the number of accesses becomes, the smaller the current consumption for a single access becomes.
Further, in the Y address priority operation, the ratio of the number of clocks needed from an activation command to a read/write command to the number of clocks for the entire operation and the ratio of the number of clocks needed from a precharge command to a next activation command to the number of clocks for the entire operation are low. This increases the ratio of data occupying the input/output (I/O) bus (data occupation rate), thereby leading to a higher efficiency of the I/O bus in the system. As the frequency of the system clock becomes higher, therefore, it is possible to increase the data occupation rate of the I/O bus in an SDRAM that needs a large latency.
There is a system which accesses an SDRAM with a shorter bit length (e.g., consecutive 4 bits, 8 bits, etc.). In an access to the SDRAM of the system, only read/write operations that have smaller than the page length are executed during a period from a single activation command to a precharge command, and the X address is changed by a next activation command. This operation is called “X address priority operation” for the sake of convenience. In the X address priority operation, sense amplifiers that are enabled by a single activation command are not used efficiently.
For example, the Y address is changed (with the X address being constant) and four memory cells are accessed. In this case, the charge/discharge current of a single word line and the current corresponding to the number of sense amplifiers (8192 sense amplifiers) to be enabled (including the charge/discharge current of the bit lines associated with the sense amplifiers) are consumed. Given that the consumed current is P(y), then the current consumed in an access to a single memory cell is P(y)/4.
In case where the X address is changed (with the Y address being arbitrary) and four memory cells are accessed, on the other hand, an activation command and a precharge command are required every time the X address is changed. In case of the access method that changes the X address, therefore, the consumed current is four times the current consumed in case of making an access with a constant X address (i.e., 4×P(y)) and the consumed current in an access to a single memory cell is P(y).
In case of a system and an application which frequently use the X address priority operation, therefore, a memory device which uses a shallow (fewer pages) Y address and a deep X address is effective. Depending on the access method of the system or a step of the application which uses a memory device, there may be a case where the X address priority operation and Y address priority operation are mixed. In this case, the use of a memory device which uses a shallow Y address makes the access speed extremely slow depending on the access order, thus hindering improvement in speed. The use of a memory device which uses a shallow X address, on the other hand, hinders reduction in consumed current.
Memory devices whose X address and Y address have different depths differ from the X address and Y address of a standard memory device in pin layout and package size, and cannot be replaced directly with the standard one. This requires that the board or the like on which the memory device is to be mounted be prepared again, thus resulting in a cost increase and longer development stage.
When an operation with large current consumption, such as the X address priority operation, is repeated, the temperature of the chip of the memory device (junction temperature) may rise. In this case, the rise in chip temperature impairs the data retaining characteristic so that the refresh operation should be performed frequently. That is, a rise in chip temperature results in a deteriorated data retaining characteristic and a further increase in consumed current originated from the frequent refresh operation. In case where the data retaining operation is executed asynchronously regardless of the control on the client system side (in case of the self-refresh operation), the refresh operation increases the busy state in which an external access is not responded. This lowers the performance of the system (the data occupation rate of the I/O bus).